library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity mux4x1 is
port(
  muxIn 	: in bus4x1;
  deadline	: in std_logic_vector (1 downto 0);
  muxOut	: out std_logic
);
end mux4x1;

architecture rtl of mux4x1 is
begin
	muxOut <= muxIn(to_integer(unsigned(deadline)));
end architecture rtl;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity clockGenerator is
port(
  mainClk 	: in std_logic;
  reset		: in std_logic;
  deadline 	: in std_logic_vector(1 downto 0);
  clk 		: out std_logic
);
end clockGenerator;

architecture rtl of clockGenerator is
component mux4x1 is
port(
  muxIn 	: in bus4x1;
  deadline	: in std_logic_vector (1 downto 0);
  muxOut	: out std_logic
);
end component;

signal counter 		: unsigned(2 downto 0);
signal muxIn		: bus4x1;
signal deadlineReg 	: std_logic_vector(1 downto 0);
signal rawClk		: std_logic;
begin
	muxIn(0)	<= mainClk;
	muxIn(1)	<= std_logic(counter(0));
	muxIn(2)	<= std_logic(counter(1));
	muxIn(3)	<= std_logic(counter(2));
	
	muxer : mux4x1 port map(muxIn,deadlineReg,rawClk);
	clk <= rawClk and (not reset);
	
	seqBlock : process (mainClk) is
	begin
		if reset = '1' then
			counter <= "000";
			deadlineReg <= "00";
		elsif rising_edge(mainClk) then
			counter <= counter + 1;
			deadlineReg <= deadline;			
		end if;
	end process seqBlock;
end architecture rtl;